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Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Fully integrated PLL, no external loop filter requirements * 1 differential 3.3V LVPECL output * Parallel resonant crystal oscillator interface * Output frequency range: 31.25MHz to 700MHz * VCO range: 250MHz to 700MHz * Parallel interface for programming counter and output dividers during power-up * Serial 3 wire interface * RMS Period jitter: 5.5ps (maximum) * Cycle-to-cycle jitter: 35ps (maximuml) * 3.3V supply voltage * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS84329B is a general purpose, single output high frequency synthesizer and a HiPerClockSTM member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the crystal frequency divided by 16. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The output can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 125kHz to 1MHz can be achieved using a 16MHz crystal depending on the output dividers.
ICS
BLOCK DIAGRAM
OE
PIN ASSIGNMENT
FOUT VCC
25 24 23 22 21 20 19 S_CLOCK 26 27 28 1 18 17 N1 N0 M8 M7 M6 M5 M4
nFOUT
TEST
VCC
VEE
VEE
XTAL_IN OSC XTAL_OUT / 16
S_DATA S_LOAD VCCA nc nc
ICS84329B
16
28-Lead PLCC 15 V Package 14 2 11.6mm x 11.4mm x 4.1mm 3 13 Top View
4 5 6
OE
PLL
PHASE DETECTOR 1 VCO /M 0 /1 /2 /4 /8
XTAL_IN
12 7
nP_LOAD
8
M0
9 10 11
M1 M2 M3
FOUT nFOUT
XTAL_OUT
nFOUT
FOUT
TEST
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
VCC
VCC
VCC
VEE
VEE
TEST
S_CLOCK S_DATA S_LOAD VCCA VCCA nc nc XTAL_IN
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23
nc N1 N0 M8 M7 M6 M5 M4
ICS84329B
22
32-Lead LQFP 21 Y package 20 7mm x 7mm x 1.4mm 19 Top View
18 17 9 10 11 12 13 14 15 16
XTAL_OUT OE nP_LOAD M0 M1 M2 M3 nc
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Integrated Circuit Systems, Inc. FUNCTIONAL DESCRIPTION
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. The TEST output is Mode 000 (shift register out) when operating in the parallel input mode. The relafxtal tionship between the VCO frequency, the crystal frequency xM and the M divider is defined as follows: fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 250 fVCO511. The M M fxtal x frequency fout = = out is defined as follows: N N 16
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS84329B features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A series-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide The programmable features of the ICS84329B support two values are latched on the HIGH-to-LOW transition of S_LOAD. input modes to program the M divider and N output divider. If S_LOAD is held HIGH, data at the S_DATA input is passed The two input operational modes are parallel and serial. Fig- directly to the M divider on each rising edge of S_CLOCK. ure 1 shows the timing diagram for each mode. In parallel mode The serial mode can be used to program the M and N bits and the nP_LOAD input is LOW. The data on inputs M0 through test bits T2:T0. The internal registers T2:T0 determine the state M8 and N0 through N1 is passed directly to the M divider and of the TEST output as follows: T2 T1 T0 TEST Output fOUT 0 0 0 Shift Register Out fOUT 0 0 1 High fOUT 0 1 0 PLL Reference Xtal / 16 fOUT 0 1 1 VCO / M fOUT (non 50% Duty M divider) 1 0 0 fOUT fOUT LVCMOS Output Frequency < 200MHz 1 0 1 Low fOUT 1 1 0 S_CLOCK / M S_CLOCK / N divider (non 50% Duty Cycle M divider) 1 1 1 fOUT / 4 fOUT
SERIAL LOADING
S_CLOCK S_DATA
t
T2
S
T1
H
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Type Description Analog supply pin. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are disabled and drive differential low: FOUT = LOW, nFOUT = HIGH. LVCMOS / LVTTL interface levels. Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and when data present at N1:N0 sets the N output divide value. LVCMOS / LVTTL interface levels. M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input. LVCMOS / LVTTL interface levels. Determines N output divider value as defined in Table 3C Function Table. LVCMOS / LVTTL interface levels. Negative supply pins. Test output which is used in the serial mode of operation. LVCMOS / LVTTL interface levels. Core supply pins. Differential output for the synthesizer. 3.3V LVPECL interface levels. Clocks the serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the M divider. LVCMOS / LVTTL interface levels. input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 1. PIN DESCRIPTIONS
Name VCCA XTAL_IN, XTAL_OUT OE Power Input Input
nP_LOAD M0, M1, M2, M3, M4, M5, M6, M7, M8 N0, N1 VEE TEST VCC nFOUT, FOUT S_CLOCK S_DATA S_LOAD
Input Input Input Power Output Power Output Input Input Input
Pullup Pullup Pullup
Pulldown Pulldown Pulldown
NOTE: Pullup and Pulldown refer to internal
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL
nP_LOAD X L H H H M X Data Data X X X
AND
SERIAL MODE FUNCTION TABLE
Inputs S_LOAD X X L L S_CLOCK X X X L L X S_DATA X X X Data Data Data X Conditions Reset. M and N bits are all set HIGH. Data on M and N inputs passed directly to M divider and N output divider. TEST mode 000. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divide and N output divide values are latched. Parallel or serial input do not affect shift registers.
N X Data Data X X X
H X X L NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency (MHz) 250 251 252 253 * * 509 510 511 M Divide 250 251 252 253 * * 509 510 511 256 M8 0 0 0 0 * * 1 1 1 128 M7 1 1 1 1 * * 1 1 1 64 M6 1 1 1 1 * * 1 1 1 32 M5 1 1 1 1 * * 1 1 1 16 M4 1 1 1 1 * * 1 1 1 8 M3 1 1 1 1 * * 1 1 1 4 M2 0 0 1 1 * * 1 1 1 2 M1 1 1 0 0 * * 0 1 1 1 M0 0 1 0 1 * * 1 0 1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 1 2 4 8 Output Frequency (MHz) Minimum 250 125 62.5 31.25 Maximum 700 35 0 175 87.5
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 37.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA ICC ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 125 15 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage M0-M8, N0, N1, OE, nP_LOAD Input High Current S_LOAD, S_DATA, S_CLOCK M0-M8, N0, N1, OE, nP_LOAD Input Low Current S_LOAD, S_DATA, S_CLOCK Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 2.6 0.5 Test Conditions Minimum Typical 2 -0.3 Maximum VCC + 0.3 0.8 5 15 0 Units V V A A A A V V
IIL VOH VOL
NOTE 1: Outputs terminated with 50 to VCC/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol VOH V OL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 10 Typical Maximum 25 50 7 1 Units MHz pF mW
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Fundamental
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol fIN Parameter Input Frequency XTAL; NOTE 1 Test Conditions Minimum 10 Typical Maximum 25 Units MHz
S_CLOCK 50 MHz NOTE 1: For the cr ystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 400 M 511. Using the maximum frequency of 25MHz valid values of M are 160 M 448.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, TA = 0C TO 70C
Symbol FOUT Parameter Output Frequency Period Jitter, RMS; NOTE 1, 2 Cycle-to-Cycle Jitter ; NOTE 1, 2 Output Rise/Fall Time Setup Time Hold Time PLL Lock Time 45 50 fOUT 65MHz fOUT < 65MHz fOUT 50MHz fOUT < 50MHz 20% to 80% 300 5 5 10 55 Test Conditions Minimum Typical Maximum 700 5.5 12 35 50 800 Units MHz ps ps ps ps ps ns ns ms %
tjit(per) tjit(cc)
tR / tF tS tH tL
odc Output Duty Cycle See Parameter Measurement Information section. Characterized using a 16MHz XTAL. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65 NOTE 2: See Applications section.
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
V CC , VCCA
Qx
SCOPE
nFOUT FOUT
tcycle
n
nQx
VEE
tjit(cc) = tcycle n -tcycle n+1
-1.3V 0.165V
1000 Cycles
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VOH VREF VOL
nFOUT FOUT
t PW
t
PERIOD
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
odc =
Histogram
t PW t PERIOD
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
S_DATA
S_CLOCK 80% Clock Outputs 80% VSW I N G 20% tR tF 20% S_LOAD
t SET-UP
t HOLD
t SET-UP
M0:M8 N0:N1
t HOLD t SET-UP
nP_LOAD
OUTPUT RISE/FALL TIME
84329BV
SETUP
AND
HOLD
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LVPECL
tcycle n+1
x 100%
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84329B provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
14
12
10
Time (pS)
8
6
4
2
0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 Output Frequency (MHz)
FIGURE 4A. RMS JITTER VS. fOUT (using a 16MHz XTAL)
60
50
40
Time (pS)
30
20
10
0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 Output Frequency (MHz)
FIGURE 4B. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
CRYSTAL INPUT INTERFACE
The ICS84329B has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 5 below were determined using a 25MHz, 18pF parallel resonant crystal and
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p ICS84332
Figure 5. CRYSTAL INPUt INTERFACE
LAYOUT GUIDELINE
The schematic of the ICS84329B layout example used in this layout guideline is shown in Figure 6A. The ICS84329B recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board.
M3 M2 M1 M0 nPLOAD OE
16MHz,18pF 11 10 9 8 7 6 5
C3 22p VCC
VCC=3 .3 V SP = S pa ce (i .e . no t in tsta ll ed ) M [8 :0 ]= 1 1 0 0 10 0 0 0 (40 0 ) N[1 :0 ] =0 1 (Di vid e b y 2 )
M4 M5 M6 M7 M8 N2 N1 12 13 14 15 16 17 18 M4 M5 M6 M7 M8 N0 N1
X1 C4 22p VCCA R7 10
M3 M2 M1 M0 nP_LOAD OE XTALOUT
U1 84329BV
19 20 21 22 23 24 25
VEE TEST VCC VEE nFOUT FOUT VCC
XTALIN nc nc VCCA S_LOAD S_DATA S_CLOCK
4 3 2 1 28 27 26
C11 0.01u
C16 10u
C1
VCC
VCC
0.1uF Zo = 50 Ohm
RU0 SP M0 M1
RU1 SP M7
RU7 1K M8
RU8 1K N0
RU9 SP N1
RU10 1K nPLoad
RU11 SP
RU12 1K
C2 0.1u Zo = 50 Ohm
Fo ut = 20 0 M Hz
OE
R2 50 RD0 1K RD1 1K RD7 SP RD8 SP RD9 1K RD10 SP RD6 1K RD12 SP R3 50
R1 50
FIGURE 6A. SCHEMATIC
84329BV
OF
RECOMMENDED LAYOUT
FOR
28 LEAD PLCC
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The following component footprints are used in this layout example: All the resistors and capacitors are size 0603.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
* The differential 50 output traces should have the same length. * Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. * Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. * To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. * Make sure no other signal traces are routed between the clock trace pair. * The matching termination resistors should be located as close to the receiver input pins as possible.
POWER
AND
GROUNDING
Place the decoupling capacitors C1, C2 and C3, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.
CLOCK TRACES
AND
TERMINATION
Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins 4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces.
X1
C3 C4
U1
GND VCC
PIN 2 PIN 1
C11
C16
VCCA
R7
VCCA
VIA
Signals Traces
C1 C2
50 Ohm Traces
FIGURE 6B. PCB BOARD LAYOUT
84329BV
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ICS84329B 28 LEAD PLCC
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Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84329B. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS84329B is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1C/W per Table 8A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.515W * 31.1C/W = 86C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE JA
FOR
28-PIN PLCC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE JA
FOR
32-PIN LQFP, FORCED CONVECTION 0 200
55.9C/W 42.1C/W
JA by Velocity (Linear Feet per Minute)
500
50.1C/W 39.4C/W Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in the Figure 7.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (V
CC_MAX
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
84329BV
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13
REV. B JUNE 10, 2005
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 9A. JAVS. AIR FLOW TABLE
FOR
28 LEAD PLCC
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 37.8C/W
200
31.1C/W
500
28.3C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 9B. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84329B is: 4408
Pin compatible with the MC12429
84329BV
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REV. B JUNE 10, 2005
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
28 LEAD PLCC
PACKAGE OUTLINE - V SUFFIX
FOR
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 4.19 2.29 1.57 0.33 0.19 12.32 11.43 4.85 12.32 11.43 4.85 MINIMUM 28 4.57 3.05 2.11 0.53 0.32 12.57 11.58 5.56 12.57 11.58 5.56 MAXIMUM
Reference Document: JEDEC Publication 95, MS-018
84329BV
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REV. B JUNE 10, 2005
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX 32 LEAD LQFP
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
84329BV
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16
REV. B JUNE 10, 2005
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Marking ICS84329BV ICS84329BV TBD TBD ICS84329BY ICS84329BY TBD TBD Package 28 Lead PLCC 28 Lead PLCC 28 Lead "Lead-Free" PLCC 28 Lead "Lead-Free" PLCC 32 Lead LQFP 32 Lead LQFP 32 Lead "Lead-Free" LQFP 32 Lead "Lead-Free" LQFP Shipping Packaging Tube 500 Tape & Reel Tube 500 Tape & Reel Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 11. ORDERING INFORMATION
Part/Order Number ICS84329BV ICS84329BVT ICS84329BVLF ICS84329BVLFT ICS84329BY ICS84329BYT ICS84329BYLF ICS84329BYLFT
NOTE: Par ts thar are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84329BV
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17
REV. B JUNE 10, 2005
Integrated Circuit Systems, Inc.
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Description of Change Features Section - added "Parallel resonant" to cr ystal bullet. Features Section - corrected Output frequency range from 25MHz to 31.25MHz. Added Lead-Free bullet. Updated Parallel & Serial Load Operations. Cr ystal Table - added Drive Level. Ordering Information Table - added Lead-Free par t numbers and note. Date 12/15/04
Rev A
Table
Page 1 1
B T5 T11
2 6 17
6/10/05
84329BV
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18
REV. B JUNE 10, 2005

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